Design of continuous-time delta-sigma modulator for sub-GHz sampling frequency

• Main Author: Tran, Xuan Anh.
• Other Authors: Tiew Kei Tee
• Format: Final Year Project
• Language: English
• Published: 2009
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• Online Access: http://hdl.handle.net/10356/15711
• Institution: Nanyang Technological University

Delta-Sigma (ΣΔ) analog-to-digital converters (ADCs) are widely used in wireless transceiver. Recently, continuous-time (CT) ΣΔ ADCs gain growing interest in their lower power consumption and wider input bandwidth as compared to the discrete-time (DT) counterparts. In this thesis, the system design and simulation of a low voltage and high frequency multi bit continuous-time (CT) sigma delta (ΣΔ) modulator is presented. It also covers the analog part of the modulator while the digital part of the modulator is covered in another thesis. The design is carried out in two stages; the first stage is the system level design of the sigma delta modulator, while the second stage is the designing of lowpass (LP) filter. The behavioral simulation of the ΣΔ modulator is done using Matlab Simulink and various non-idealities such as excess loop delay, clock jitter and DAC nonlinearity are modeled and studied. The LP filter is designed using transconductor-capacitor (Gm-C) opamp integrator and RC opamp integrator. The proposed CT delta-sigma modulator is a third-order continuous-time multi-bit (4-bit) modulator intended to operate at an oversampling ratio of 16. Simulation results show that the modulator achieves more than 80dB dynamic range over a 16-MHz bandwidth with a sampling frequency of 512MHz. This device is designed and simulated in 0.18µm CMOS process technology using Cadence IC design software.