High speed CMOS multiplier design
Due to increasing popularity of real-time systems, there is an increasing need for high-speed circuits to process data and deliver an output for subsequent circuits to be used. A multiplier is a type of circuit crucial in processing data and generally the slowest in the system. To implement a h...
Saved in:
| 主要作者: | |
|---|---|
| 其他作者: | |
| 格式: | Final Year Project |
| 語言: | English |
| 出版: |
Nanyang Technological University
2022
|
| 主題: | |
| 在線閱讀: | https://hdl.handle.net/10356/157386 |
| 標簽: |
添加標簽
沒有標簽, 成為第一個標記此記錄!
|
| 總結: | Due to increasing popularity of real-time systems, there is an increasing need for high-speed
circuits to process data and deliver an output for subsequent circuits to be used. A multiplier is
a type of circuit crucial in processing data and generally the slowest in the system.
To implement a high-speed CMOS multiplier, we would have to consider its circuit design
which comprises of its logic gates. By using different types of logic combinations, we can
achieve the function of a multiplier. The speed of the multiplier would be affected by the delay
of the logic circuit. This would be achieved by using Verilog to design the circuit and Synopsys
to synthesize the circuit. The different designs will be analysed, and the delay of the output
compared. The proposed multiplier design is about 2 times faster than the array multiplier. The
simulations are performed using AMS 0.35um technology. |
|---|