CMOS capacitor multiplier

• Main Author: Mirea Iulian.
• Other Authors: Chan Pak Kwong
• Format: Theses and Dissertations
• Language: English
• Published: 2009
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: http://hdl.handle.net/10356/18813
• Institution: Nanyang Technological University

A new circuit topology for a grounded capacitor multiplier has been proposed. The main goal is to practically implement a high multiplication factor for capacitance in view of device mismatching and power consumption. Power by a supply of 3.3 V, the proposed circuit is implemented using CSM CMOS 0....