CMOS capacitor multiplier

• Main Author: Mirea Iulian.
• Other Authors: Chan Pak Kwong
• Format: Theses and Dissertations
• Language: English
• Published: 2009
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: http://hdl.handle.net/10356/18813
• Institution: Nanyang Technological University

A new circuit topology for a grounded capacitor multiplier has been proposed. The main goal is to practically implement a high multiplication factor for capacitance in view of device mismatching and power consumption. Power by a supply of 3.3 V, the proposed circuit is implemented using CSM CMOS 0.18μm process technology. Different versions (40X, 40X-LP, 400X) of the capacitance multiplier are presented,, with maximum capacitance multiplication factor up to 400. Two new figures of merits (FOMs) to quantify the performance of capacitor multipliers are proposed. Performance comparison to the prior-art circuit has shown that the 400X version multiplier has similar level of power efficiency but yet displaying much reduced output offset current for a broad frequency range when compared to the respective FOM. This is thank for the novel capacitance multiplier topology that improves the performance. However, there exists possible headroom for realizing higher multiplication factor over almost 4 decades of frequency operation. More importantly, a lower input offset current can be achieved based on same device mismatch. This permits the capacitor multiplier to be driven by lower power circuits that do not need to have high current capabilities to cover for high input current offset. Ultimately, this will make toe topology more usable in real life application circuits.