Low power digital multiplier IC design

• Main Author: Hu, Qigang
• Other Authors: Gwee Bah Hwee
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2022
• Subjects: Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/162497
• Institution: Nanyang Technological University

As an important part of the digital signal processor, the speed of the multiplier directly determines the performance of the entire processor. This dissertation fully provided a design of 16-bit low power digital multiplier. This dissertation first introduced the development of multipliers and the binary format. Subsequently, it implemented the commonly used algorithms. Thereafter, it gave more details about several circuits for generating partial products, 4:2 compressors and several typical multi-bit adders and multipliers. Then, it proposed a multiplier design architecture based on Booth algorithm. Finally, this dissertation presented the simulation, Synthesis, and power consumption simulation results of this multiplier. This design was based on the AMS 0.35 Technology library, using Verilog HDL to compile, the VCS software to perform verification and power simulation, and the DC software to synthesis. The delay of this multiplier is 3.51ns, the area of multiplier is 59260 μm2, and the power consumption of this multiplier is 5.3004 mW. As shown in these data, the multiplier achieved the expected objective and meet the specification.