High-performance CMOS digital multiplier IC design

A digital multiplier is a common block in processors, and its speed has a significant impact on the performance of the chip. Many new design ideas have emerged around how to improve the speed of multipliers, including pipeline structure, Wallace Tree structure, and Booth encoding. The Wallace Tree s...

Full description

Saved in:
Bibliographic Details
Main Author: Chu, Zhuolin
Other Authors: Gwee Bah Hwee
Format: Thesis-Master by Coursework
Language:English
Published: Nanyang Technological University 2023
Subjects:
Online Access:https://hdl.handle.net/10356/164473
Tags: Add Tag
No Tags, Be the first to tag this record!
Institution: Nanyang Technological University
Language: English