High-performance CMOS digital multiplier IC design

• Main Author: Chu, Zhuolin
• Other Authors: Gwee Bah Hwee
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2023
• Subjects: Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/164473
• Institution: Nanyang Technological University

A digital multiplier is a common block in processors, and its speed has a significant impact on the performance of the chip. Many new design ideas have emerged around how to improve the speed of multipliers, including pipeline structure, Wallace Tree structure, and Booth encoding. The Wallace Tree structure increases the speed of partial product summation by compressing the number of partial products; A Carry-look-ahead Adder can be greatly optimized for the addition of multi-bit numbers, and it skips the lengthy bit-by-bit carry propagation process, dramatically increasing the speed of addition operations. Meanwhile, it also reduces the power consumption of the adding circuit by reducing the number of full adders and half adders. Combining the two yields a multiplier with very little circuit propagation delay and power consumption. This project proposes a 16-bit high-speed and low-power CMOS digital multiplier, which uses a Wallace Tree structure and a 24-bit carry-look-ahead adder unit to implement. Simulation, synthesis, and power analysis are based on the STM065 library. The final result shows that there is a 23% reduction in latency and 69% reduction in power consumption without much increase in area compared to a conventional multiplier with a Wallace tree structure. The overall PDP is reduced by 76%, which shows that the performance of the multiplier proposed in this project was significantly outperformed the conventional multipliers.