A formal methodology for verifying side-channel vulnerabilities in cache architectures

• Main Authors: Jiang, Ke, Zhang, Tianwei, Sanan, David, Zhao, Yongwang, Liu, Yang
• Other Authors: School of Computer Science and Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2023
• Subjects: Engineering::Computer science and engineering; Cache Designs; Side-Channel Attacks; Security Verification
• Online Access: https://hdl.handle.net/10356/165417
• Institution: Nanyang Technological University

Security-aware CPU caches have been designed to mitigate side-channel attacks and prevent information leakage. How to validate the effectiveness of these designs remains an unsolved problem. Prior works assess the security of architectures empirically without a formal guarantee, making the evaluatio...