Developing secure, ultra-low power RISC processor

Technology is becoming much more prevalent in the lives of many, mostly in the form of Internet of Things devices. A common feature in IoT devices is the ability to perform firmware over-the-air updates so as to able to introduce new functionality to existing devices. These firmware over-the-air upd...

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Main Author: Ang, Kai Jun
Other Authors: Anupam Chattopadhyay
Format: Final Year Project
Language:English
Published: Nanyang Technological University 2023
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Online Access:https://hdl.handle.net/10356/165949
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-1659492023-04-21T15:37:33Z Developing secure, ultra-low power RISC processor Ang, Kai Jun Anupam Chattopadhyay School of Computer Science and Engineering anupam@ntu.edu.sg Engineering::Computer science and engineering Technology is becoming much more prevalent in the lives of many, mostly in the form of Internet of Things devices. A common feature in IoT devices is the ability to perform firmware over-the-air updates so as to able to introduce new functionality to existing devices. These firmware over-the-air updates are currently using only classical cryptography algorithms for security. While this may be sufficient for now, it may not be in the future. Quantum Computing is a growing field and post-quantum algorithms capable of breaking certain classical cryptography algorithms have been developed. While there is yet to be a sufficiently powerful quantum computer to run these algorithms, it is vital that existing protocols using only classical cryptography be updated to include quantum resistant cryptography. This project aims to develop a hybrid implementation of the firmware over-the-air update process, incorporating both classical and post-quantum cryptography. The project was successful in developing a hybrid implementation that is able to verify digital signatures from both a classical and a post quantum cryptography algorithm. This project, however, was unable to complete the entirety of the firmware over-the-air update process, falling short of implementing the bootloader code. Bachelor of Engineering (Computer Engineering) 2023-04-17T06:56:01Z 2023-04-17T06:56:01Z 2023 Final Year Project (FYP) Ang, K. J. (2023). Developing secure, ultra-low power RISC processor. Final Year Project (FYP), Nanyang Technological University, Singapore. https://hdl.handle.net/10356/165949 https://hdl.handle.net/10356/165949 en SCSE22-0032 application/pdf Nanyang Technological University
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic Engineering::Computer science and engineering
spellingShingle Engineering::Computer science and engineering
Ang, Kai Jun
Developing secure, ultra-low power RISC processor
description Technology is becoming much more prevalent in the lives of many, mostly in the form of Internet of Things devices. A common feature in IoT devices is the ability to perform firmware over-the-air updates so as to able to introduce new functionality to existing devices. These firmware over-the-air updates are currently using only classical cryptography algorithms for security. While this may be sufficient for now, it may not be in the future. Quantum Computing is a growing field and post-quantum algorithms capable of breaking certain classical cryptography algorithms have been developed. While there is yet to be a sufficiently powerful quantum computer to run these algorithms, it is vital that existing protocols using only classical cryptography be updated to include quantum resistant cryptography. This project aims to develop a hybrid implementation of the firmware over-the-air update process, incorporating both classical and post-quantum cryptography. The project was successful in developing a hybrid implementation that is able to verify digital signatures from both a classical and a post quantum cryptography algorithm. This project, however, was unable to complete the entirety of the firmware over-the-air update process, falling short of implementing the bootloader code.
author2 Anupam Chattopadhyay
author_facet Anupam Chattopadhyay
Ang, Kai Jun
format Final Year Project
author Ang, Kai Jun
author_sort Ang, Kai Jun
title Developing secure, ultra-low power RISC processor
title_short Developing secure, ultra-low power RISC processor
title_full Developing secure, ultra-low power RISC processor
title_fullStr Developing secure, ultra-low power RISC processor
title_full_unstemmed Developing secure, ultra-low power RISC processor
title_sort developing secure, ultra-low power risc processor
publisher Nanyang Technological University
publishDate 2023
url https://hdl.handle.net/10356/165949
_version_ 1764208094673371136