Design of memory controllers and input/output controller for low-voltage asynchronous digital signal processor

• Main Author: Low, Joshua Yung Lih.
• Other Authors: Gwee Bah Hwee
• Format: Final Year Project
• Language: English
• Published: 2009
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Control and instrumentation::Control engineering
• Online Access: http://hdl.handle.net/10356/16698
• Institution: Nanyang Technological University

This project encompasses the generation of memory blocks, design and implementation of memory and input/output (IO) controllers for a low voltage (1.25V) asynchronous DSP56002 design. DSP56002, from the DSP56K Family, is Motorola’s series of 24-bit general purpose Digital Signal Processor. There are three memory blocks generated using Artisan Standard Library 130nm SRAM Generator from ARM®. These memories are dual-port SRAMs and they serve as program memory, x-data memory and y-data memory respectively for the asynchronous DSP56002 design to establish a complete asynchronous DSP56002 system. In this project, three asynchronous memory controllers and one IO controller are designed. The memory controllers, based on 4-phase bundled data protocol, enable the communication between the synchronous memories and the asynchronous DSP56002 core. On the other hand, the IO controller multiplexes 60 signals (3 control signals and 57 data signals) from the each memory and 28 signals (4 control signals and 24 data signals) from DSP56002 core onto 39 signals (5 control signals and 34 data signals) at the interface to the external environment. The tool, Petrify, is used in the specification capturing and synthesis design stages while Mentor Graphic® Modelsim® is used for functional simulation and verification purposes. Lastly, non-timing driven placement and routing (PAR) of the complete asynchronous DSP56002 system is carried out using Cadence® Soc Encounter™ RTL-to-GDSII System version 6.2 with IBM130nm CMOS technology. This PAR process which is performed until the stage of post route timing analysis and optimization involves 3 hard macro blocks (memory blocks) and multiple supply voltage (MSV) features. During PAR, the complete asynchronous DSP system is segregated into three power domains to enable a separate measurement of currents to different parts of the circuit and hence provide a better understanding of power distribution.