Interface design of high speed ADC based on FPGA
With the continuous improvement of communication technology, the data transmission rate is increasing rapidly. At present, many high-speed application scenarios such as 5G communication, automatic driving, radar, aerospace, and high-precision instrumentation are eager for more high-speed and stable...
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| Format: | Thesis-Master by Coursework |
| Language: | English |
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Nanyang Technological University
2023
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| Online Access: | https://hdl.handle.net/10356/168002 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | With the continuous improvement of communication technology, the data transmission rate is increasing rapidly. At present, many high-speed application scenarios such as 5G communication, automatic driving, radar, aerospace, and high-precision instrumentation are eager for more high-speed and stable serial data interfaces. In order to meet the needs of data-intensive applications to process data faster, experts and scholars from various countries have begun to use various methods to study it.
This dissertation designs the interface of high-speed ADC based on FPGA, and proposes a digital IP module for pulse data detection and clock domain transmission, which can effectively read the data of high-speed ADC more stably and accurately, and achieved relatively good results in actual simulation and testing. |
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