Efficient FPGA-based sparse matrix-vector multiplication with data reuse-aware compression
Sparse matrix-vector multiplication (SpMV) on FPGAs has gained much attention. The performance of SpMV is mainly determined by the number of multiplications between non-zero matrix elements and the corresponding vector values per cycle. On the one side, the off-chip memory bandwidth limits the numbe...
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Main Authors: | , , |
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Format: | Article |
Language: | English |
Published: |
2023
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Online Access: | https://hdl.handle.net/10356/169152 |
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Institution: | Nanyang Technological University |
Language: | English |