Efficient FPGA-based sparse matrix-vector multiplication with data reuse-aware compression
Sparse matrix-vector multiplication (SpMV) on FPGAs has gained much attention. The performance of SpMV is mainly determined by the number of multiplications between non-zero matrix elements and the corresponding vector values per cycle. On the one side, the off-chip memory bandwidth limits the numbe...
Saved in:
Main Authors: | Li, Shiqing, Liu, Di, Liu, Weichen |
---|---|
Other Authors: | School of Computer Science and Engineering |
Format: | Article |
Language: | English |
Published: |
2023
|
Subjects: | |
Online Access: | https://hdl.handle.net/10356/169152 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | Nanyang Technological University |
Language: | English |
Similar Items
-
An efficient gustavson-based sparse matrix-matrix multiplication accelerator on embedded FPGAs
by: Li, Shiqing, et al.
Published: (2023) -
Accelerating gustavson-based SpMM on embedded FPGAs with element-wise parallelism and access pattern-aware caches
by: Li, Shiqing, et al.
Published: (2023) -
Optimized data reuse via reordering for sparse matrix-vector multiplication on FPGAs
by: Li, Shiqing, et al.
Published: (2022) -
Solve Ax=B on an FPGA
by: Ling, Jun Han
Published: (2024) -
Looting the LUTs : FPGA optimization of AES and AES-like ciphers for authenticated encryption
by: Khairallah, Mustafa, et al.
Published: (2020)