Heterogeneous dataflow architectures for FPGA-based sparse LU factorization

FPGA-based token dataflow architectures with heterogeneous computation and communication subsystems can accelerate hard-to-parallelize, irregular computations in sparse LU factorization. We combine software pre-processing and architecture customization to fully expose and exploit the underlying hete...

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書目詳細資料
Main Authors: Siddhartha, Kapre, Nachiket
其他作者: School of Computer Engineering
格式: Conference or Workshop Item
語言:English
出版: 2015
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在線閱讀:https://hdl.handle.net/10356/81188
http://hdl.handle.net/10220/39175
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