Accelerating sparse matrix operations on FPGAs with on/off-chip memories

Sparse matrix operations on FPGAs have gained much attention. Since sparse matrix operations are memory-bounded, the hardware efficiency depends on hardware-aware data organization and dedicated hardware design. On the one side, sparse matrices are stored in the off-chip DDR and are transferred to t...

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Bibliographic Details
Main Author: Li, Shiqing
Other Authors: Weichen Liu
Format: Thesis-Doctor of Philosophy
Language:English
Published: Nanyang Technological University 2023
Subjects:
Online Access:https://hdl.handle.net/10356/172513
https://doi.org/10.21979/N9/ATEYFB
https://doi.org/10.21979/N9/EXZ0Y3
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Institution: Nanyang Technological University
Language: English