Accelerating sparse matrix operations on FPGAs with on/off-chip memories
Sparse matrix operations on FPGAs have gained much attention. Since sparse matrix operations are memory-bounded, the hardware efficiency depends on hardware-aware data organization and dedicated hardware design. On the one side, sparse matrices are stored in the off-chip DDR and are transferred to t...
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| Format: | Thesis-Doctor of Philosophy |
| Language: | English |
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Nanyang Technological University
2023
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| Online Access: | https://hdl.handle.net/10356/172513 https://doi.org/10.21979/N9/ATEYFB https://doi.org/10.21979/N9/EXZ0Y3 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | Sparse matrix operations on FPGAs have gained much attention. Since sparse matrix operations are memory-bounded, the hardware efficiency depends on hardware-aware data organization and dedicated hardware design. On the one side, sparse matrices are stored in the off-chip DDR and are transferred to the FPGA chip via the off-chip memory bandwidth. To reduce the bandwidth requirement, sparse matrices are stored using compressed formats. However, previous compressed formats do not consider full and efficient utilization of the off-chip memory bandwidth. On the other hand, efficient hardware designs are required to process compressed data. Especially, well-organized on-chip memories can buffer reusable data and mitigate the off-chip memory bandwidth requirement. In this thesis, we mainly target sparse-matrix dense-vector multiplication (SpMV), Sparse-matrix sparse-matrix multiplication (SpMM), and sparse Long short-term memory (SpLSTM). Experimental results on Xilinx ZCU106 and PYNQ-Z1 show considerable performance speedup. |
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