Ultra-high-speed accelerator architecture for convolutional neural network based on processing-in-memory using resistive random access memory

• Main Authors: Wang, Hongzhe, Wang, Junjie, Hu, Hao, Li, Guo, Hu, Shaogang, Yu, Qi, Liu, Zhen, Chen, Tupei, Zhou, Shijie, Liu, Yang
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2023
• Subjects: Engineering::Electrical and electronic engineering; RRAM; Convolutional Neural Network
• Online Access: https://hdl.handle.net/10356/169464
• Institution: Nanyang Technological University

Processing-in-Memory (PIM) based on Resistive Random Access Memory (RRAM) is an emerging acceleration architecture for artificial neural networks. This paper proposes an RRAM PIM accelerator architecture that does not use Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs). Additionally, no additional memory usage is required to avoid the need for a large amount of data transportation in convolution computation. Partial quantization is introduced to reduce the accuracy loss. The proposed architecture can substantially reduce the overall power consumption and accelerate computation. The simulation results show that the image recognition rate for the Convolutional Neural Network (CNN) algorithm can reach 284 frames per second at 50 MHz using this architecture. The accuracy of the partial quantization remains almost unchanged compared to the algorithm without quantization.