A new reconfigurable true random number generator and physical unclonable function unified chip with on-chip auto-calibration
True random number generator (TRNG) and physical unclonable function (PUF) have been extensively used to secure low-cost Internet of Things (IoT) endpoints. In this paper, a lightweight reconfigurable TRNG and PUF unified design for custom chip implementation is proposed. The reconfigurable stru...
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Main Authors: | , , , , , , |
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Other Authors: | |
Format: | Article |
Language: | English |
Published: |
2023
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Subjects: | |
Online Access: | https://hdl.handle.net/10356/170732 |
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Institution: | Nanyang Technological University |
Language: | English |
Summary: | True random number generator (TRNG) and physical unclonable function (PUF) have been extensively used to
secure low-cost Internet of Things (IoT) endpoints. In this paper,
a lightweight reconfigurable TRNG and PUF unified design for
custom chip implementation is proposed. The reconfigurable
structure consists of a pair of ring oscillators (ROs) with
interposed multi-way switches for RO length reconfiguration and
shared counters for on-chip calibration. Jitter noise of ROs and
metastability of arbiter are harmonized for TRNG operation,
while process variations of ROs are extracted for PUF operation.
The conflicting requirements on frequency deviation for the
randomness of TRNG and the reliability of PUF are resolved
by an on-chip calibrator, which automatically selects and stores
a challenge with a small frequency difference in TRNG mode
upon manufacturing and masks unreliable challenges with large
frequency difference during PUF enrollment. Leveraging the
advantage of custom chip design, the basic delay cell of the reconfigurable ROs is realized by current starved inverter in weak
inversion to minimize the power consumption, increase the jitter,
and avail its larger process variation. A new lightweight secure
mutual authentication protocol is also proposed to effectively
thwart machine learning, replay and man-in-the-middle attacks
using only the underlying TRNG and PUF without requiring
any other security primitives. The proposed TRNG-PUF design
is prototyped with a standard 40 nm 1.1 V CMOS process. It
occupies a small footprint of 24,316 µm2
. Measured results of the packaged chips show an average energy efficiency of 7.42
pJ/bit in TRNG operation and 0.10 pJ/bit in PUF operation. The
bitstreams generated by the test chips passed NIST SP 800-22
and 90B tests, autocorrelation test, and FFT test. |
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