A new reconfigurable true random number generator and physical unclonable function unified chip with on-chip auto-calibration

True random number generator (TRNG) and physical unclonable function (PUF) have been extensively used to secure low-cost Internet of Things (IoT) endpoints. In this paper, a lightweight reconfigurable TRNG and PUF unified design for custom chip implementation is proposed. The reconfigurable stru...

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Main Authors: Cao, Yuan, Liu, Wanyi, Zheng, Yue, Chen, Shuai, Ye, Jing, Qian, Lei, Chang, Chip Hong
Other Authors: School of Electrical and Electronic Engineering
Format: Article
Language:English
Published: 2023
Subjects:
Online Access:https://hdl.handle.net/10356/170732
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Institution: Nanyang Technological University
Language: English
id sg-ntu-dr.10356-170732
record_format dspace
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic Engineering::Electrical and electronic engineering::Integrated circuits
True Random Number Generator
Physical Unclonable Function
Current-Starved Ring Oscillator
spellingShingle Engineering::Electrical and electronic engineering::Integrated circuits
True Random Number Generator
Physical Unclonable Function
Current-Starved Ring Oscillator
Cao, Yuan
Liu, Wanyi
Zheng, Yue
Chen, Shuai
Ye, Jing
Qian, Lei
Chang, Chip Hong
A new reconfigurable true random number generator and physical unclonable function unified chip with on-chip auto-calibration
description True random number generator (TRNG) and physical unclonable function (PUF) have been extensively used to secure low-cost Internet of Things (IoT) endpoints. In this paper, a lightweight reconfigurable TRNG and PUF unified design for custom chip implementation is proposed. The reconfigurable structure consists of a pair of ring oscillators (ROs) with interposed multi-way switches for RO length reconfiguration and shared counters for on-chip calibration. Jitter noise of ROs and metastability of arbiter are harmonized for TRNG operation, while process variations of ROs are extracted for PUF operation. The conflicting requirements on frequency deviation for the randomness of TRNG and the reliability of PUF are resolved by an on-chip calibrator, which automatically selects and stores a challenge with a small frequency difference in TRNG mode upon manufacturing and masks unreliable challenges with large frequency difference during PUF enrollment. Leveraging the advantage of custom chip design, the basic delay cell of the reconfigurable ROs is realized by current starved inverter in weak inversion to minimize the power consumption, increase the jitter, and avail its larger process variation. A new lightweight secure mutual authentication protocol is also proposed to effectively thwart machine learning, replay and man-in-the-middle attacks using only the underlying TRNG and PUF without requiring any other security primitives. The proposed TRNG-PUF design is prototyped with a standard 40 nm 1.1 V CMOS process. It occupies a small footprint of 24,316 µm2 . Measured results of the packaged chips show an average energy efficiency of 7.42 pJ/bit in TRNG operation and 0.10 pJ/bit in PUF operation. The bitstreams generated by the test chips passed NIST SP 800-22 and 90B tests, autocorrelation test, and FFT test.
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
Cao, Yuan
Liu, Wanyi
Zheng, Yue
Chen, Shuai
Ye, Jing
Qian, Lei
Chang, Chip Hong
format Article
author Cao, Yuan
Liu, Wanyi
Zheng, Yue
Chen, Shuai
Ye, Jing
Qian, Lei
Chang, Chip Hong
author_sort Cao, Yuan
title A new reconfigurable true random number generator and physical unclonable function unified chip with on-chip auto-calibration
title_short A new reconfigurable true random number generator and physical unclonable function unified chip with on-chip auto-calibration
title_full A new reconfigurable true random number generator and physical unclonable function unified chip with on-chip auto-calibration
title_fullStr A new reconfigurable true random number generator and physical unclonable function unified chip with on-chip auto-calibration
title_full_unstemmed A new reconfigurable true random number generator and physical unclonable function unified chip with on-chip auto-calibration
title_sort new reconfigurable true random number generator and physical unclonable function unified chip with on-chip auto-calibration
publishDate 2023
url https://hdl.handle.net/10356/170732
_version_ 1779156811044093952
spelling sg-ntu-dr.10356-1707322023-09-29T15:40:11Z A new reconfigurable true random number generator and physical unclonable function unified chip with on-chip auto-calibration Cao, Yuan Liu, Wanyi Zheng, Yue Chen, Shuai Ye, Jing Qian, Lei Chang, Chip Hong School of Electrical and Electronic Engineering Engineering::Electrical and electronic engineering::Integrated circuits True Random Number Generator Physical Unclonable Function Current-Starved Ring Oscillator True random number generator (TRNG) and physical unclonable function (PUF) have been extensively used to secure low-cost Internet of Things (IoT) endpoints. In this paper, a lightweight reconfigurable TRNG and PUF unified design for custom chip implementation is proposed. The reconfigurable structure consists of a pair of ring oscillators (ROs) with interposed multi-way switches for RO length reconfiguration and shared counters for on-chip calibration. Jitter noise of ROs and metastability of arbiter are harmonized for TRNG operation, while process variations of ROs are extracted for PUF operation. The conflicting requirements on frequency deviation for the randomness of TRNG and the reliability of PUF are resolved by an on-chip calibrator, which automatically selects and stores a challenge with a small frequency difference in TRNG mode upon manufacturing and masks unreliable challenges with large frequency difference during PUF enrollment. Leveraging the advantage of custom chip design, the basic delay cell of the reconfigurable ROs is realized by current starved inverter in weak inversion to minimize the power consumption, increase the jitter, and avail its larger process variation. A new lightweight secure mutual authentication protocol is also proposed to effectively thwart machine learning, replay and man-in-the-middle attacks using only the underlying TRNG and PUF without requiring any other security primitives. The proposed TRNG-PUF design is prototyped with a standard 40 nm 1.1 V CMOS process. It occupies a small footprint of 24,316 µm2 . Measured results of the packaged chips show an average energy efficiency of 7.42 pJ/bit in TRNG operation and 0.10 pJ/bit in PUF operation. The bitstreams generated by the test chips passed NIST SP 800-22 and 90B tests, autocorrelation test, and FFT test. Ministry of Education (MOE) Submitted/Accepted version This work was supported in part by the Ministry of Education, Singapore, under its AcRF Tier 2 under Award MOET2EP50220-0003; in part by the Fundamental Research Funds for Natural Science Foundation of Jiangsu Province under Grant BK20191160; in part by the Open Research of the State Key Laboratory of Computer Architecture under Grant CARCH201901; in part by the QingLan Project, Changzhou Science and Technology Program under Grant CJ20200071 and Grant 2020029; in part by the National Natural Science Foundation of China under Grant 62274056; in part by the Open Fund of Advanced Cryptography and System Security Key Laboratory of Sichuan Province under Grant SKLACSS-202209; in part by the Key Research and Development Program of Jiangsu Province under Grant BE2022098; and in part by the Postdoctoral Science Foundation of Jiangsu Province under Grant 2021K605C. 2023-09-29T02:17:13Z 2023-09-29T02:17:13Z 2023 Journal Article Cao, Y., Liu, W., Zheng, Y., Chen, S., Ye, J., Qian, L. & Chang, C. H. (2023). A new reconfigurable true random number generator and physical unclonable function unified chip with on-chip auto-calibration. IEEE Transactions On Circuits and Systems I: Regular Papers. https://dx.doi.org/10.1109/TCSI.2023.3316890 1549-8328 https://hdl.handle.net/10356/170732 10.1109/TCSI.2023.3316890 en MOET2EP50220-0003 IEEE Transactions on Circuits and Systems I: Regular Papers © 2023 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/TCSI.2023.3316890. application/pdf