Design and implementation of asynchronous low power sub-threshold memory circuit

• Main Author: Khor, Boon Pin.
• Other Authors: Gwee Bah Hwee
• Format: Final Year Project
• Language: English
• Published: 2009
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: http://hdl.handle.net/10356/17163
• Institution: Nanyang Technological University

This project presents the design and implementation of a low-power asynchronous memory circuit operating in subthreshold region down to 0.2V. The memory circuit will be employed in a low-power asynchronous subthreshold FIR filter. The purposes of this project are to investigate the power and energy dissipation as well as signal propagation delay time of the memory circuit operation at subthreshold region using IBM 0.13µm CMRF8SF process technology Low Power (LP) transistor model. The design and simulation of the memory circuit uses Synopsys NanoSim and Cadence Virtuoso. First, a SPICE file circuit netlist is created and simulated using NanoSim. Subsequently, the schematic and layout of the circuit is built using Virtuoso. The goal for this project is to ensure that the memory circuit operates robustly at 0.2V. The simulation result shows that using IBM 0.13µm CMRF8SF LP transistor model, the memory circuit can operate robustly at 0.18V, with average power dissipation of 22pW, write delay 212µs and read delay 215µs. A SRAM memory circuit is designed and simulated to benchmark the performance of the proposed memory circuit. The SRAM memory circuit works as low as 0.42V. The proposed asynchronous low power subthreshold memory circuit can operate at much lower operating voltage (0.18V) compared to conventional SRAM. Another benchmark circuit is the same circuit design using IBM 0.13µm CMRF8SF Regular Threshold Voltage (RVT) transistor model. Using RVT transistor, the circuit operates at 0.18V with average power dissipation of 2911pW, write delay 1483ns and read delay 1803ns. LP transistor model has a low power dissipation (22pW) advantage over RVT transistor model.