A novel design of power-efficient reconfigurable multiplier targeting at increasing the throughput of the CGRA
In the dynamic world of artificial intelligence (AI) with escalating computational needs, the significance of edge computing has risen. Edge computing emphasizes local computations on devices, particularly using Software-Defined Chip (SDC) such as the Coarse-Grained Reconfigurable Architecture (CGRA...
Saved in:
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Thesis-Master by Coursework |
| Language: | English |
| Published: |
Nanyang Technological University
2023
|
| Online Access: | https://hdl.handle.net/10356/171880 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Institution: | Nanyang Technological University |
| Language: | English |
Be the first to leave a comment!