A digital IP design of ADC interface based on FPGA

• 主要作者: Zhai, Ke
• 其他作者: Zheng Yuanjin
• 格式: Thesis-Master by Coursework
• 語言: English
• 出版: Nanyang Technological University 2023
• 主題: Engineering::Electrical and electronic engineering::Integrated circuits
• 在線閱讀: https://hdl.handle.net/10356/171898
• 機構: Nanyang Technological University

FPGA, as an important branch of integrated circuits, has the advantage of rapid circuit development without the need for type-out, and has been widely used in the fields of image processing, artificial intelligence, etc. The FPGA input/output interface is a bridge for data interaction between the FPGA chip and the peripheral chips, and the interface logic, as the core part of the interface, directly affects the transmission rate and stability of the peripheral chips such as high-speed memory and the FPGA chip, so the design of the FPGA input/output interface logic is of particular importance. As the core part of the interface, the interface logic will directly affect the transmission rate and stability of the peripheral chips such as high-speed memory and FPGA chips, so the design of the input/output interface logic of FPGA is particularly important. In this thesis, based on the SGGROUP school-enterprise cooperation project, a high speed ADC-FPGA interface is designed, which has several modules of data processing, filtering, cross-clock domain and storage, and utilizes two asynchronous FIFOs for ping pong operation to efficiently handle the data, and it has a good performance. Through the simulation and verification, we found that the interface can effectively transmit data across the clock domain, and the data obtained is stable and effective, which achieves the design results.