High speed AES encryption IC design

• Main Author: Dong, Haokun
• Other Authors: Gwee Bah Hwee
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2024
• Subjects: Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: https://hdl.handle.net/10356/173060
• Institution: Nanyang Technological University

In the current data-driven landscape, efficiency and accuracy are prioritized, frequently at the expense of data security considerations. Hardware devices like Graphics processing unit (GPU), Central processing unit (CPU), FPGA tend to utilize encryption as a solution to protect the data. However, these hardware components are vulnerable to Side-Channel Attack (SCA) due to potential information leakage. To mitigate this risk, this dissertation introduces the concept of threshold implementation. Threshold implementation could enhance the performance by dividing sensitive information, like the secret key and intermediate values, into multiple shares. Advanced Encryption Standard (AES) is widely used in all kinds of applications. Therefore, it is critical to ensure that the efficiency of encryption speed is balanced with information security, especially for scenarios that demand quick response and fast data transmission, such as E-commerce and server communication. In this dissertation, an improved AES using threshold implementation technique in S-box is implemented to FPGA boards to test its performance through 3 main steps. The first step is building the S-box by decomposing S-box process into 2 cubic permutations. The second step involves designing the remaining operations for each round. The third step is to set testbench and simulate the results to compare the design overheads for security. The simulation results show that the resources (LUTs, registers, slices) were reduced by 73.25%, 87.24% and 71.67% respectively. Furthermore, the AES implementation can be adapted to smaller FPGAs by using half-pipeline and quarter-pipeline.