High speed AES encryption IC design

In the current data-driven landscape, efficiency and accuracy are prioritized, frequently at the expense of data security considerations. Hardware devices like Graphics processing unit (GPU), Central processing unit (CPU), FPGA tend to utilize encryption as a solution to protect the data. However, t...

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Main Author: Dong, Haokun
Other Authors: Gwee Bah Hwee
Format: Thesis-Master by Coursework
Language:English
Published: Nanyang Technological University 2024
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Online Access:https://hdl.handle.net/10356/173060
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-1730602024-01-12T15:46:07Z High speed AES encryption IC design Dong, Haokun Gwee Bah Hwee School of Electrical and Electronic Engineering ebhgwee@ntu.edu.sg Engineering::Electrical and electronic engineering::Integrated circuits In the current data-driven landscape, efficiency and accuracy are prioritized, frequently at the expense of data security considerations. Hardware devices like Graphics processing unit (GPU), Central processing unit (CPU), FPGA tend to utilize encryption as a solution to protect the data. However, these hardware components are vulnerable to Side-Channel Attack (SCA) due to potential information leakage. To mitigate this risk, this dissertation introduces the concept of threshold implementation. Threshold implementation could enhance the performance by dividing sensitive information, like the secret key and intermediate values, into multiple shares. Advanced Encryption Standard (AES) is widely used in all kinds of applications. Therefore, it is critical to ensure that the efficiency of encryption speed is balanced with information security, especially for scenarios that demand quick response and fast data transmission, such as E-commerce and server communication. In this dissertation, an improved AES using threshold implementation technique in S-box is implemented to FPGA boards to test its performance through 3 main steps. The first step is building the S-box by decomposing S-box process into 2 cubic permutations. The second step involves designing the remaining operations for each round. The third step is to set testbench and simulate the results to compare the design overheads for security. The simulation results show that the resources (LUTs, registers, slices) were reduced by 73.25%, 87.24% and 71.67% respectively. Furthermore, the AES implementation can be adapted to smaller FPGAs by using half-pipeline and quarter-pipeline. Master's degree 2024-01-10T08:00:06Z 2024-01-10T08:00:06Z 2024 Thesis-Master by Coursework Dong, H. (2024). High speed AES encryption IC design. Master's thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/173060 https://hdl.handle.net/10356/173060 en application/pdf Nanyang Technological University
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic Engineering::Electrical and electronic engineering::Integrated circuits
spellingShingle Engineering::Electrical and electronic engineering::Integrated circuits
Dong, Haokun
High speed AES encryption IC design
description In the current data-driven landscape, efficiency and accuracy are prioritized, frequently at the expense of data security considerations. Hardware devices like Graphics processing unit (GPU), Central processing unit (CPU), FPGA tend to utilize encryption as a solution to protect the data. However, these hardware components are vulnerable to Side-Channel Attack (SCA) due to potential information leakage. To mitigate this risk, this dissertation introduces the concept of threshold implementation. Threshold implementation could enhance the performance by dividing sensitive information, like the secret key and intermediate values, into multiple shares. Advanced Encryption Standard (AES) is widely used in all kinds of applications. Therefore, it is critical to ensure that the efficiency of encryption speed is balanced with information security, especially for scenarios that demand quick response and fast data transmission, such as E-commerce and server communication. In this dissertation, an improved AES using threshold implementation technique in S-box is implemented to FPGA boards to test its performance through 3 main steps. The first step is building the S-box by decomposing S-box process into 2 cubic permutations. The second step involves designing the remaining operations for each round. The third step is to set testbench and simulate the results to compare the design overheads for security. The simulation results show that the resources (LUTs, registers, slices) were reduced by 73.25%, 87.24% and 71.67% respectively. Furthermore, the AES implementation can be adapted to smaller FPGAs by using half-pipeline and quarter-pipeline.
author2 Gwee Bah Hwee
author_facet Gwee Bah Hwee
Dong, Haokun
format Thesis-Master by Coursework
author Dong, Haokun
author_sort Dong, Haokun
title High speed AES encryption IC design
title_short High speed AES encryption IC design
title_full High speed AES encryption IC design
title_fullStr High speed AES encryption IC design
title_full_unstemmed High speed AES encryption IC design
title_sort high speed aes encryption ic design
publisher Nanyang Technological University
publishDate 2024
url https://hdl.handle.net/10356/173060
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