Deep-learning-based X-ray CT slice analysis for layout verification in printed circuit boards
3D X-ray Computational Tomography (CT) systems have been employed to inspect Printed Circuit Boards (PCB) for security analysis, considering the heightened trustworthiness concern on the globalized supply chain. In this paper, we propose a deep-learning-based layout verification (DELVer) framework t...
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sg-ntu-dr.10356-1738582024-03-07T15:31:49Z Deep-learning-based X-ray CT slice analysis for layout verification in printed circuit boards Cheng, Deruo Shi, Yiqiong Tee, Yee Yang Song, Jingsi Wang, Xue Wen, Bihan Gwee, Bah Hwee School of Electrical and Electronic Engineering 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS) Temasek Laboratories Engineering Printed circuit boards Hardware security 3D X-ray Computational Tomography (CT) systems have been employed to inspect Printed Circuit Boards (PCB) for security analysis, considering the heightened trustworthiness concern on the globalized supply chain. In this paper, we propose a deep-learning-based layout verification (DELVer) framework to automatically extract PCB layout information from X-ray CT slices and verify against the design files. Leveraging on geometrical projective transformation, our proposed DELVer framework aligns the acquired CT slice of each PCB layer with their corresponding design file, to train state-of-the-art deep learning models for layout extraction and verification. It thus alleviates the laborious manual data labeling for deep learning models. With a cross-device evaluation on 4 multi-layer satellite PCBs of board size around 90 cm2, our proposed DELVer framework demonstrates how deep learning models can generalize to unseen target PCBs for layout verification, establishing an efficient solution for PCB assurance and industrial failure analysis. National Research Foundation (NRF) Submitted/Accepted version This research is supported by the National Research Foundation, Singapore, under its National Cybersecurity Research & Development Programme / Cyber-Hardware Forensic & Assurance Evaluation R&D Programme (Award: NRF2018NCRNCR009-0001). 2024-03-06T07:45:23Z 2024-03-06T07:45:23Z 2023 Conference Paper Cheng, D., Shi, Y., Tee, Y. Y., Song, J., Wang, X., Wen, B. & Gwee, B. H. (2023). Deep-learning-based X-ray CT slice analysis for layout verification in printed circuit boards. 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS). https://dx.doi.org/10.1109/AICAS57966.2023.10168608 9798350332674 2834-9857 https://hdl.handle.net/10356/173858 10.1109/AICAS57966.2023.10168608 2-s2.0-85166377000 en NRF2018NCRNCR009-0001 © 2023 IEEE. All rights reserved. This article may be downloaded for personal use only. Any other use requires prior permission of the copyright holder. The Version of Record is available online at http://doi.org/10.1109/AICAS57966.2023.10168608. application/pdf |
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Engineering Printed circuit boards Hardware security Cheng, Deruo Shi, Yiqiong Tee, Yee Yang Song, Jingsi Wang, Xue Wen, Bihan Gwee, Bah Hwee Deep-learning-based X-ray CT slice analysis for layout verification in printed circuit boards |
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3D X-ray Computational Tomography (CT) systems have been employed to inspect Printed Circuit Boards (PCB) for security analysis, considering the heightened trustworthiness concern on the globalized supply chain. In this paper, we propose a deep-learning-based layout verification (DELVer) framework to automatically extract PCB layout information from X-ray CT slices and verify against the design files. Leveraging on geometrical projective transformation, our proposed DELVer framework aligns the acquired CT slice of each PCB layer with their corresponding design file, to train state-of-the-art deep learning models for layout extraction and verification. It thus alleviates the laborious manual data labeling for deep learning models. With a cross-device evaluation on 4 multi-layer satellite PCBs of board size around 90 cm2, our proposed DELVer framework demonstrates how deep learning models can generalize to unseen target PCBs for layout verification, establishing an efficient solution for PCB assurance and industrial failure analysis. |
author2 |
School of Electrical and Electronic Engineering |
author_facet |
School of Electrical and Electronic Engineering Cheng, Deruo Shi, Yiqiong Tee, Yee Yang Song, Jingsi Wang, Xue Wen, Bihan Gwee, Bah Hwee |
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Conference or Workshop Item |
author |
Cheng, Deruo Shi, Yiqiong Tee, Yee Yang Song, Jingsi Wang, Xue Wen, Bihan Gwee, Bah Hwee |
author_sort |
Cheng, Deruo |
title |
Deep-learning-based X-ray CT slice analysis for layout verification in printed circuit boards |
title_short |
Deep-learning-based X-ray CT slice analysis for layout verification in printed circuit boards |
title_full |
Deep-learning-based X-ray CT slice analysis for layout verification in printed circuit boards |
title_fullStr |
Deep-learning-based X-ray CT slice analysis for layout verification in printed circuit boards |
title_full_unstemmed |
Deep-learning-based X-ray CT slice analysis for layout verification in printed circuit boards |
title_sort |
deep-learning-based x-ray ct slice analysis for layout verification in printed circuit boards |
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2024 |
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https://hdl.handle.net/10356/173858 |
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1794549361659609088 |