APB bus LPTIM verification based on universal verification methodology

• Main Author: Yao, Junxin
• Other Authors: Kim Tae Hyoung
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2024
• Subjects: Engineering; Low-power timer; Universal verification methodology; Microcontroller unit; System on chip; Constrained-randomization; Directed test
• Online Access: https://hdl.handle.net/10356/174148
• Institution: Nanyang Technological University

With the complexity and scale of the chip growing exponentially every generation, the need for verification resources has greatly increased. The common method is using SystemVerilog and Universal Verification Methodology (UVM) to build a verification environment and accomplish the verification. Due to the components in the environment being derived from uvm_components, the reusability is largely enhanced by utilizing Universal Verification Methodology (UVM). Since the digital chip has an architecture containing many modules, sometimes the verification of one single module is not enough. The system-level verification is required. Reducing power consumption is a mainstream of the development of Microcontroller Unit (MCU) and System on Chip (SoC). In this thesis, the Low-Power Timer (LPTIM) is verified with its functionalities and low-power features. The UPF regression is all passed, indicating that the LPTIM is correctly working in the low-power mode. Using 68 testcases, all the features are tested, and the code coverage is 100%. A few testcases formulations are explained in detail and the waveform results are also reviewed.