APB bus LPTIM verification based on universal verification methodology

• Main Author: Yao, Junxin
• Other Authors: Kim Tae Hyoung
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2024
• Subjects: Engineering; Low-power timer; Universal verification methodology; Microcontroller unit; System on chip; Constrained-randomization; Directed test
• Online Access: https://hdl.handle.net/10356/174148
• Institution: Nanyang Technological University

With the complexity and scale of the chip growing exponentially every generation, the need for verification resources has greatly increased. The common method is using SystemVerilog and Universal Verification Methodology (UVM) to build a verification environment and accomplish the verification. Due...