A 16-bit single-OTA second-order discrete time delta-sigma modulator with improved noise-coupling technique

• Main Author: Zhang, Siqi
• Other Authors: Goh Wang Ling
• Format: Final Year Project
• Language: English
• Published: Nanyang Technological University 2024
• Subjects: Engineering; Delta-sigma modulator; Analog-to-digital converter
• Online Access: https://hdl.handle.net/10356/176220
• Institution: Nanyang Technological University

This report presents a low-power second-order Discrete-Time (DT) Delta-Sigma Modulator (DSM) for Internet of Things (IoT) applications. The design is based on the Noise Coupling (NC) structure, which has the advantage of fewer amplifiers, lower harmonics, and reduced idle tones. However, the NC structure requires multibit quantizers in the filter loop, resulting in an increase in circuit complexity and power. This work improves the conventional NC structure with additional dual feedback paths to suppress the high-frequency gain of the noise transfer function (NTF), thereby reducing the internal voltage swing and relaxing the requirement of the quantizer resolution. The improved structure is simulated and analyzed in MATLAB Simulink, and is proved to be efficient. In addition, a stage-sharing technique is implemented in the circuit, so that a single Operational Transconductance Amplifier (OTA) is shared by two stages separately to realize the function of both integrating and adding. Hence, second-order noise shaping is achieved with only a single OTA. Analog components, especially OTA, consume the most power in the DSM. The decreasing number of OTAs significantly reduces the power consumption. Implemented in a 130nm CMOS process, the proposed design demonstrated a simulated SNDR of 99.8dB in a 10kHz bandwidth with a 5.12MS/s sampling rate, consuming 200μW. It also achieved an outstanding SFDR of 105.1dB, indicating its high linearity. State-of-the-art Schreier FoM (SNDR) and Walden FoM of 176.8dB and 125fJ/conv-step are achieved, which is among the best of all reported second-order DSMs. The outcomes have been accepted by IEEE 2024 International Symposium on Circuits and Systems.