A 16-bit single-OTA second-order discrete time delta-sigma modulator with improved noise-coupling technique

This report presents a low-power second-order Discrete-Time (DT) Delta-Sigma Modulator (DSM) for Internet of Things (IoT) applications. The design is based on the Noise Coupling (NC) structure, which has the advantage of fewer amplifiers, lower harmonics, and reduced idle tones. However, the NC stru...

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Main Author: Zhang, Siqi
Other Authors: Goh Wang Ling
Format: Final Year Project
Language:English
Published: Nanyang Technological University 2024
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Online Access:https://hdl.handle.net/10356/176220
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spelling sg-ntu-dr.10356-1762202024-05-17T15:44:29Z A 16-bit single-OTA second-order discrete time delta-sigma modulator with improved noise-coupling technique Zhang, Siqi Goh Wang Ling School of Electrical and Electronic Engineering A*STAR Institute of Microelectronics EWLGOH@ntu.edu.sg Engineering Delta-sigma modulator Analog-to-digital converter This report presents a low-power second-order Discrete-Time (DT) Delta-Sigma Modulator (DSM) for Internet of Things (IoT) applications. The design is based on the Noise Coupling (NC) structure, which has the advantage of fewer amplifiers, lower harmonics, and reduced idle tones. However, the NC structure requires multibit quantizers in the filter loop, resulting in an increase in circuit complexity and power. This work improves the conventional NC structure with additional dual feedback paths to suppress the high-frequency gain of the noise transfer function (NTF), thereby reducing the internal voltage swing and relaxing the requirement of the quantizer resolution. The improved structure is simulated and analyzed in MATLAB Simulink, and is proved to be efficient. In addition, a stage-sharing technique is implemented in the circuit, so that a single Operational Transconductance Amplifier (OTA) is shared by two stages separately to realize the function of both integrating and adding. Hence, second-order noise shaping is achieved with only a single OTA. Analog components, especially OTA, consume the most power in the DSM. The decreasing number of OTAs significantly reduces the power consumption. Implemented in a 130nm CMOS process, the proposed design demonstrated a simulated SNDR of 99.8dB in a 10kHz bandwidth with a 5.12MS/s sampling rate, consuming 200μW. It also achieved an outstanding SFDR of 105.1dB, indicating its high linearity. State-of-the-art Schreier FoM (SNDR) and Walden FoM of 176.8dB and 125fJ/conv-step are achieved, which is among the best of all reported second-order DSMs. The outcomes have been accepted by IEEE 2024 International Symposium on Circuits and Systems. Bachelor's degree 2024-05-15T01:39:09Z 2024-05-15T01:39:09Z 2024 Final Year Project (FYP) Zhang, S. (2024). A 16-bit single-OTA second-order discrete time delta-sigma modulator with improved noise-coupling technique. Final Year Project (FYP), Nanyang Technological University, Singapore. https://hdl.handle.net/10356/176220 https://hdl.handle.net/10356/176220 en B2330-231 application/pdf Nanyang Technological University
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic Engineering
Delta-sigma modulator
Analog-to-digital converter
spellingShingle Engineering
Delta-sigma modulator
Analog-to-digital converter
Zhang, Siqi
A 16-bit single-OTA second-order discrete time delta-sigma modulator with improved noise-coupling technique
description This report presents a low-power second-order Discrete-Time (DT) Delta-Sigma Modulator (DSM) for Internet of Things (IoT) applications. The design is based on the Noise Coupling (NC) structure, which has the advantage of fewer amplifiers, lower harmonics, and reduced idle tones. However, the NC structure requires multibit quantizers in the filter loop, resulting in an increase in circuit complexity and power. This work improves the conventional NC structure with additional dual feedback paths to suppress the high-frequency gain of the noise transfer function (NTF), thereby reducing the internal voltage swing and relaxing the requirement of the quantizer resolution. The improved structure is simulated and analyzed in MATLAB Simulink, and is proved to be efficient. In addition, a stage-sharing technique is implemented in the circuit, so that a single Operational Transconductance Amplifier (OTA) is shared by two stages separately to realize the function of both integrating and adding. Hence, second-order noise shaping is achieved with only a single OTA. Analog components, especially OTA, consume the most power in the DSM. The decreasing number of OTAs significantly reduces the power consumption. Implemented in a 130nm CMOS process, the proposed design demonstrated a simulated SNDR of 99.8dB in a 10kHz bandwidth with a 5.12MS/s sampling rate, consuming 200μW. It also achieved an outstanding SFDR of 105.1dB, indicating its high linearity. State-of-the-art Schreier FoM (SNDR) and Walden FoM of 176.8dB and 125fJ/conv-step are achieved, which is among the best of all reported second-order DSMs. The outcomes have been accepted by IEEE 2024 International Symposium on Circuits and Systems.
author2 Goh Wang Ling
author_facet Goh Wang Ling
Zhang, Siqi
format Final Year Project
author Zhang, Siqi
author_sort Zhang, Siqi
title A 16-bit single-OTA second-order discrete time delta-sigma modulator with improved noise-coupling technique
title_short A 16-bit single-OTA second-order discrete time delta-sigma modulator with improved noise-coupling technique
title_full A 16-bit single-OTA second-order discrete time delta-sigma modulator with improved noise-coupling technique
title_fullStr A 16-bit single-OTA second-order discrete time delta-sigma modulator with improved noise-coupling technique
title_full_unstemmed A 16-bit single-OTA second-order discrete time delta-sigma modulator with improved noise-coupling technique
title_sort 16-bit single-ota second-order discrete time delta-sigma modulator with improved noise-coupling technique
publisher Nanyang Technological University
publishDate 2024
url https://hdl.handle.net/10356/176220
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