CLAHE HLS implementation on Zynq SoC FPGA

CLAHE HLS implementation on Zynq SoC FPGA

Infrared (IR) imaging is pivotal for military applications, facilitating detection in low-light scenarios. However, conventional IR images often suffer from contrast issues, particularly when displaying high and low-temperature objects in the same scene. This leads to a loss of contrast in the whole...

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Main Author: Yoong, Nathaniel Khai Jie
Other Authors: Radhakrishnan K
Format: Final Year Project
Language:English
Published: Nanyang Technological University 2024
Subjects:
Engineering
CLAHE
HLS
FPGA
Online Access:https://hdl.handle.net/10356/176412
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Institution: Nanyang Technological University
Language: English
id sg-ntu-dr.10356-176412
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spelling sg-ntu-dr.10356-1764122024-05-17T15:43:50Z CLAHE HLS implementation on Zynq SoC FPGA Yoong, Nathaniel Khai Jie Radhakrishnan K School of Electrical and Electronic Engineering DSO National Laboratories ERADHA@ntu.edu.sg Engineering CLAHE HLS FPGA Infrared (IR) imaging is pivotal for military applications, facilitating detection in low-light scenarios. However, conventional IR images often suffer from contrast issues, particularly when displaying high and low-temperature objects in the same scene. This leads to a loss of contrast in the whole image. Contrast Limiting Adaptive Histogram Equalization (CLAHE) emerges as a solution, enhancing image quality by segmenting the image into tiles and applying histogram equalization techniques. This paper proposes the implementation of CLAHE on a Field Programmable Gate Array (FPGA), leveraging its real-time data processing capabilities. By employing High-Level Synthesis (HLS), the algorithm's execution on FPGA promises significant contrast enhancement, surpassing conventional methods like histogram equalization. The envisioned FPGA-based CLAHE system aims to offer superior IR image contrast crucial for military surveillance and reconnaissance applications Bachelor's degree 2024-05-16T12:13:37Z 2024-05-16T12:13:37Z 2024 Final Year Project (FYP) Yoong, N. K. J. (2024). CLAHE HLS implementation on Zynq SoC FPGA. Final Year Project (FYP), Nanyang Technological University, Singapore. https://hdl.handle.net/10356/176412 https://hdl.handle.net/10356/176412 en application/pdf Nanyang Technological University
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic Engineering
CLAHE
HLS
FPGA
spellingShingle Engineering
CLAHE
HLS
FPGA
Yoong, Nathaniel Khai Jie
CLAHE HLS implementation on Zynq SoC FPGA
description Infrared (IR) imaging is pivotal for military applications, facilitating detection in low-light scenarios. However, conventional IR images often suffer from contrast issues, particularly when displaying high and low-temperature objects in the same scene. This leads to a loss of contrast in the whole image. Contrast Limiting Adaptive Histogram Equalization (CLAHE) emerges as a solution, enhancing image quality by segmenting the image into tiles and applying histogram equalization techniques. This paper proposes the implementation of CLAHE on a Field Programmable Gate Array (FPGA), leveraging its real-time data processing capabilities. By employing High-Level Synthesis (HLS), the algorithm's execution on FPGA promises significant contrast enhancement, surpassing conventional methods like histogram equalization. The envisioned FPGA-based CLAHE system aims to offer superior IR image contrast crucial for military surveillance and reconnaissance applications
author2 Radhakrishnan K
author_facet Radhakrishnan K
Yoong, Nathaniel Khai Jie
format Final Year Project
author Yoong, Nathaniel Khai Jie
author_sort Yoong, Nathaniel Khai Jie
title CLAHE HLS implementation on Zynq SoC FPGA
title_short CLAHE HLS implementation on Zynq SoC FPGA
title_full CLAHE HLS implementation on Zynq SoC FPGA
title_fullStr CLAHE HLS implementation on Zynq SoC FPGA
title_full_unstemmed CLAHE HLS implementation on Zynq SoC FPGA
title_sort clahe hls implementation on zynq soc fpga
publisher Nanyang Technological University
publishDate 2024
url https://hdl.handle.net/10356/176412
_version_ 1800916102555893760

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