Solve Ax=B on an FPGA
This report describes the development and analysis of a hardware-accelerated Gaussian Elimination linear solver implemented on the PYNQ-Z1 Field Programmable Gate Array (FPGA) System on Chip (SOC). The primary intention was to explore the potential of FPGAs to accelerate computational tasks speci...
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Format: | Final Year Project |
Language: | English |
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Nanyang Technological University
2024
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Online Access: | https://hdl.handle.net/10356/176485 |
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Institution: | Nanyang Technological University |
Language: | English |
Summary: | This report describes the development and analysis of a hardware-accelerated Gaussian
Elimination linear solver implemented on the PYNQ-Z1 Field Programmable Gate Array (FPGA)
System on Chip (SOC). The primary intention was to explore the potential of FPGAs to accelerate
computational tasks specifically mathematical calculations traditionally performed by software
and leverage the parallel processing capabilities of the PYNQ Z1 platform. The project also intends
to address and overcome the challenges and limitations of hardware acceleration specifically the
memory transfer bottlenecks which is known source of throughput limitation for hardware
acceleration.
By presenting a comprehensive overview of the project’s design and implementation process,
along with the encountered obstacles, with a detailed exploration of the problem, including the
potential causes and workarounds.
Despite the promising capabilities of FPGAs in enhancing computational speed, the project
encountered a significant obstacle during the final stages of implementation, with the Direct
Memory Access (DMA) integration. Through a detailed examination of the project’s design, this
report discusses the encountered memory transfer bottleneck, emphasizing on the DMA-related
challenge that posed a critical impediment. Additionally, it explores the theoretical solutions and
workarounds for overcoming such limitations in FPGA-based projects.
The project concluded with a successful design and implementation of a 128 by 128 floating point
Gaussian Elimination solver implemented onto FPGA hardware, the PYNQ Z1, that processed the input data correctly and by measurements of the processing function’s run time, outperformed a software solution running on the same processing system. |
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