Solve Ax=B on an FPGA

This report describes the development and analysis of a hardware-accelerated Gaussian Elimination linear solver implemented on the PYNQ-Z1 Field Programmable Gate Array (FPGA) System on Chip (SOC). The primary intention was to explore the potential of FPGAs to accelerate computational tasks speci...

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Main Author: Ling, Jun Han
Other Authors: Ling Keck Voon
Format: Final Year Project
Language:English
Published: Nanyang Technological University 2024
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Online Access:https://hdl.handle.net/10356/176485
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-1764852024-05-17T15:45:39Z Solve Ax=B on an FPGA Ling, Jun Han Ling Keck Voon School of Electrical and Electronic Engineering EKVLING@ntu.edu.sg Engineering FPGA This report describes the development and analysis of a hardware-accelerated Gaussian Elimination linear solver implemented on the PYNQ-Z1 Field Programmable Gate Array (FPGA) System on Chip (SOC). The primary intention was to explore the potential of FPGAs to accelerate computational tasks specifically mathematical calculations traditionally performed by software and leverage the parallel processing capabilities of the PYNQ Z1 platform. The project also intends to address and overcome the challenges and limitations of hardware acceleration specifically the memory transfer bottlenecks which is known source of throughput limitation for hardware acceleration. By presenting a comprehensive overview of the project’s design and implementation process, along with the encountered obstacles, with a detailed exploration of the problem, including the potential causes and workarounds. Despite the promising capabilities of FPGAs in enhancing computational speed, the project encountered a significant obstacle during the final stages of implementation, with the Direct Memory Access (DMA) integration. Through a detailed examination of the project’s design, this report discusses the encountered memory transfer bottleneck, emphasizing on the DMA-related challenge that posed a critical impediment. Additionally, it explores the theoretical solutions and workarounds for overcoming such limitations in FPGA-based projects. The project concluded with a successful design and implementation of a 128 by 128 floating point Gaussian Elimination solver implemented onto FPGA hardware, the PYNQ Z1, that processed the input data correctly and by measurements of the processing function’s run time, outperformed a software solution running on the same processing system. Bachelor's degree 2024-05-17T02:22:38Z 2024-05-17T02:22:38Z 2024 Final Year Project (FYP) Ling, J. H. (2024). Solve Ax=B on an FPGA. Final Year Project (FYP), Nanyang Technological University, Singapore. https://hdl.handle.net/10356/176485 https://hdl.handle.net/10356/176485 en A1078-231 application/pdf Nanyang Technological University
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic Engineering
FPGA
spellingShingle Engineering
FPGA
Ling, Jun Han
Solve Ax=B on an FPGA
description This report describes the development and analysis of a hardware-accelerated Gaussian Elimination linear solver implemented on the PYNQ-Z1 Field Programmable Gate Array (FPGA) System on Chip (SOC). The primary intention was to explore the potential of FPGAs to accelerate computational tasks specifically mathematical calculations traditionally performed by software and leverage the parallel processing capabilities of the PYNQ Z1 platform. The project also intends to address and overcome the challenges and limitations of hardware acceleration specifically the memory transfer bottlenecks which is known source of throughput limitation for hardware acceleration. By presenting a comprehensive overview of the project’s design and implementation process, along with the encountered obstacles, with a detailed exploration of the problem, including the potential causes and workarounds. Despite the promising capabilities of FPGAs in enhancing computational speed, the project encountered a significant obstacle during the final stages of implementation, with the Direct Memory Access (DMA) integration. Through a detailed examination of the project’s design, this report discusses the encountered memory transfer bottleneck, emphasizing on the DMA-related challenge that posed a critical impediment. Additionally, it explores the theoretical solutions and workarounds for overcoming such limitations in FPGA-based projects. The project concluded with a successful design and implementation of a 128 by 128 floating point Gaussian Elimination solver implemented onto FPGA hardware, the PYNQ Z1, that processed the input data correctly and by measurements of the processing function’s run time, outperformed a software solution running on the same processing system.
author2 Ling Keck Voon
author_facet Ling Keck Voon
Ling, Jun Han
format Final Year Project
author Ling, Jun Han
author_sort Ling, Jun Han
title Solve Ax=B on an FPGA
title_short Solve Ax=B on an FPGA
title_full Solve Ax=B on an FPGA
title_fullStr Solve Ax=B on an FPGA
title_full_unstemmed Solve Ax=B on an FPGA
title_sort solve ax=b on an fpga
publisher Nanyang Technological University
publishDate 2024
url https://hdl.handle.net/10356/176485
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