Variation tolerant sensing circuits for resistive memory

• Main Author: Chong, Yu Ze
• Other Authors: Kim Tae Hyoung
• Format: Final Year Project
• Language: English
• Published: Nanyang Technological University 2024
• Subjects: Engineering; Resistive memory
• Online Access: https://hdl.handle.net/10356/176605
• Institution: Nanyang Technological University

Resistive memory is gaining its popularity as an alternative to the flash in non-volatile memory owing to several significant advantages. However, resistive fluctuations due to resistive layer within ReRAM and fabrication process affect the performance of ReRAM. Therefore, various sensing schemes are studied so that ReRAM is resilient to resistance fluctuations. In this project, Offset-Compensated Voltage Sensing Amplifier is designed to mitigate the effect of process mismatch due to process threshold voltage, V_th of the transistor. It is designed using GF 40nm technology and simulated on Cadence software. Then, OC-VSA is integrated into ReRAM memory array to simulate the read operation. Results show that the OC-VSA is able to achieve bit line sensing time as low as 3.33 ns before introducing read error. OC-VSA is tolerant towards process variation and temperature through Monte Carlo sampling and temperature sweep.