Low-voltage low-power (LVLP) scalable voltage reference
In recent years, with the continuous advancement of integrated circuit, there has been a significant surge in the demand for low voltage design. Voltage references, being integral components in numerous electronic systems, play a pivotal role in ensuring accurate and reliable operation, such as the...
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Format: | Final Year Project |
Language: | English |
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Nanyang Technological University
2024
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Online Access: | https://hdl.handle.net/10356/176843 |
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Institution: | Nanyang Technological University |
Language: | English |
Summary: | In recent years, with the continuous advancement of integrated circuit, there has been a significant surge in the demand for low voltage design. Voltage references, being integral components in numerous electronic systems, play a pivotal role in ensuring accurate and reliable operation, such as the central processing units (CPU), the low dropout regulators (LDO), the analog-to-digital converters (ADC). It leverages precision voltage generation techniques such as bandgap references, can effectively mitigate voltage variations due to temperature fluctuations and provide stable voltage outputs, thus meeting the stringent requirements of various applications in electronics. Nevertheless, with the shrinking and advancing of the CMOS technology, the conducting voltage of the bipolar transistor limits the decreasing of the input voltage, thus, the sub-threshold MOS voltage reference design has become a trend in the state-of-arts research due to it can cater a lower input voltage.
This thesis presents a Low-Voltage Low-Power (LVLP) saleable voltage reference without the use of the parasitic vertical PNP, based on 2 Transistor(2T) bandgap core. The proposed voltage reference using Global Foundry (GF) 55nm CMOS process technology, it can work under supply voltage from 1.15V to 0.55V. At designed Vdd 0.9V, the voltage reference achieved minimum 1.837ppm temperature coefficient (TC), 0.057% line regulation (LR) and -66.24dB power supply rejection ratio (PSRR). Another design version with sizing optimization is also presented to cater a low supply voltage range from 0.7V to 0.5V. At 0.5V supply voltage, it consumes only 16.35nW and the minimum TC of 2.02ppm. It also has -46.63dB PSRR with low dropout of 200mV.
Index terms: voltage reference, sub-MOS design, low input voltage, low power. |
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