8 bit asynchronous SAR ADC
In this project, we propose the design of an 8-bit Asynchronous Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). This ADC is engineered to resolve signals up to 100 MHz and can perform conversions at a clock speed of 200 MHz. The ADC is optimized for low power consumption,...
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| 格式: | Final Year Project |
| 語言: | English |
| 出版: |
Nanyang Technological University
2024
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| 主題: | |
| 在線閱讀: | https://hdl.handle.net/10356/177191 |
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| 機構: | Nanyang Technological University |
| 語言: | English |
| 總結: | In this project, we propose the design of an 8-bit Asynchronous Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). This ADC is engineered to resolve signals up to 100 MHz and can perform conversions at a clock speed of 200 MHz. The ADC is optimized for low power consumption, operating within a power supply range of 1.8 to 1.5V, and features a reference voltage set at 1V.
The schematic for this integrated circuit was developed using the 55nm CMOS Process Development Kit (PDK) from Global Foundries. The design and circuit simulation were carried out using the Cadence® Virtuoso® Analog Design Environment (ADE)-L.
The architecture of the ADC enables asynchronous operation of its various blocks within a single clock cycle, employing a feed-forward configuration. In this setup, the determination of the values for subsequent lower significant bits is influenced by the values of higher significant bits. The ADC has been rigorously tested to function reliably within a temperature range of -20°C to 60°C and across various process corners. |
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