The design of a CMOS only low-power low-voltage low-dropout voltage regulator (LDO) with an embedded voltage reference
This report presented a transient-enhanced low dropout voltage (LDO) regulator with an integrated push-pull composite power transistor and an embedded voltage reference (VR). The use of a composite power transistor shifts parasitic poles to higher frequencies, enhancing stability. A recycling folded...
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| Format: | Final Year Project |
| Language: | English |
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Nanyang Technological University
2024
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| Online Access: | https://hdl.handle.net/10356/178418 |
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| Summary: | This report presented a transient-enhanced low dropout voltage (LDO) regulator with an integrated push-pull composite power transistor and an embedded voltage reference (VR). The use of a composite power transistor shifts parasitic poles to higher frequencies, enhancing stability. A recycling folded cascode (RFC) amplifier achieves higher loop gain, improving load and line regulation. A recovery time enhancement circuit reduces overshoot recovery. The VR employs various resistor types for high-order compensation, with trimming ensuring stable performance across corners. Implemented in GF 55nm technology, the LDO operates at 1V to 1.2V input voltage, delivering up to 50mA current with less than 200mV dropout. It consumes 43.85μA quiescent current, settles within 1μA, and exhibits excellent line regulation (3.76mV/V), load regulation (0.0076mA/mV), and PSRR (-44dB @ 1KHz). |
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