Design and evaluation of high-level estimation and optimization techniques for power consumption

• Main Author: Lee, Sheanwei.
• Other Authors: Gwee Bah Hwee
• Format: Final Year Project
• Language: English
• Published: 2009
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Power electronics
• Online Access: http://hdl.handle.net/10356/17879
• Institution: Nanyang Technological University

This report presents design and evaluation of High-Level Estimation and Optimization Techniques for Power Consumption. Power dissipation has become increasingly more important as a design constraint as factors such as growing portable devices market, reliability, cooling and packaging are given a heavier consideration when designing ICs. By obtaining estimation of power consumption at higher levels of abstraction, designers are able to optimize and reduce power consumption more significantly and thus reducing design iteration time. In this project, we investigated the characterization based macro modeling technique by building a power model using information of lower level implementations. Replicating the steps taken, we have determined the inputs used are in normal binary format rather than 2’s complement binary. At the same time, the steps taken were automated whenever possible. Finally, the model was verified against the results from Synopsys Nanosim and an accuracy of 8.07% was obtained.