Low power digital multiplier IC design

• Main Author: Luo, Weiran
• Other Authors: Gwee Bah Hwee
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2025
• Subjects: Computer and Information Science
• Online Access: https://hdl.handle.net/10356/182231
• Institution: Nanyang Technological University

Multipliers constitute a crucial component of integrated circuits and are extensively employed in the realm of digital signal processing. The performance of multipliers frequently dictates the overall performance of circuits and devices. Reducing the power consumption of multipliers represents a significant aspect of optimizing their design. This dissertation initially introduces the principles of multipliers and delves into several prevalent multiplier structures and algorithmic principles, such as the carry-save adder, 3:2 compressor, and Booth algorithm. Subsequently, an optimized low-power structure is proposed, accompanied by its simulation and synthesis results. The comprehensive findings are presented in a format of reports. This design is compiled with Verilog HDL, verified, and power simulated using VCS software, and synthesized with DC software. The multiplier occupies an area of 41197 μm2 and consumes 3.4251 mW of power. As evident from these figures, the multiplier has met the anticipated objectives and aligns with the specifications.