16-bit high-speed CMOS multiplier IC design

• Main Author: Feng, Haotian
• Other Authors: Gwee Bah Hwee
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2025
• Subjects: Engineering; 16-bit multiplier; Vedic algorithm; Booth algorithm; Wallace-tree; CMOS ST 65nm; High-speed design
• Online Access: https://hdl.handle.net/10356/182449
• Institution: Nanyang Technological University

This dissertation focuses on a high-speed 16-bit CMOS multiplier design. In order to satisfy the increasing demands of contemporary computing systems, multiplication—a basic operation in digital signal processing, cryptography, and arithmetic units—needs to be implemented efficiently in hardwa...