Mixed-signal integrated circuits for neuromorphic computing
In neuromorphic computing, the traditional von Neumann architecture faces efficiency bottlenecks due to the frequent data transfers between memory and processors. This limitation has provided an opportunity for the development of IMC architectures. RRAM, as a mature non-volatile memory device, is wi...
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| Format: | Thesis-Master by Coursework |
| Language: | English |
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Nanyang Technological University
2025
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| Online Access: | https://hdl.handle.net/10356/182693 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | In neuromorphic computing, the traditional von Neumann architecture faces efficiency bottlenecks due to the frequent data transfers between memory and processors. This limitation has provided an opportunity for the development of IMC architectures. RRAM, as a mature non-volatile memory device, is widely used in IMC architectures and can accommodate an intrinsic impedance boosting technique to effectively suppress output distortion. This paper presents the design of mixed-signal integrated circuits to convert the MAC computation results of an RRAM array into digital outputs. The integrated circuit utilizes an 8-bit SAR
ADC structure, designed on a 40nm technology node using Cadence, which can achieve a sampling rate of 66.7 MHz. Under simulation conditions of 27°C and a 1 V power supply, the designed ADC achieved an ENOB of 7.80 bits, a DNL of +0.4/-0.2, and an INL of +0.4/-0.3. The total power consumption was measured at 89.18 µW, with the FOMW and FOMS reaching 6 fJ/conv-step and 167.46 dB, respectively. |
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