Wire level encapsulation framework for increasing FPGA design productivity

This thesis explores the performance impact of optimising the components of a Field Programmable Gate Array (FPGA) system down to the lowest level independently from other parts of the system. The motivation for this is that not only is the design and verification effort put in to a component reused...

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Bibliographic Details
Main Author: Oliver, Timothy Francis
Other Authors: Douglas Leslie Maskell
Format: Theses and Dissertations
Language:English
Published: 2009
Subjects:
Online Access:https://hdl.handle.net/10356/19266
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Institution: Nanyang Technological University
Language: English