Computer-aided fault analysis of digital circuit

• Main Author: Yip, Chee Soon.
• Other Authors: Chin, Edward Hsi Ling
• Format: Theses and Dissertations
• Language: English
• Published: 2009
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• Online Access: http://hdl.handle.net/10356/19814
• Institution: Nanyang Technological University

Two test pattern generation programs are developed - bd and MoDalg. The bd implements the boolean difference method, an algebraic method that manipulates boolean equations to derive a complete test set for all possible stuck-at faults in the circuit under test.