Asynchronous circuit compiler design

• 主要作者: Tan, Lik Sin.
• 其他作者: Gwee Bah Hwee
• 格式: Final Year Project
• 語言: English
• 出版: 2010
• 主題: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• 在線閱讀: http://hdl.handle.net/10356/20773
• 機構: Nanyang Technological University

The report has elaborated the Final Year Project (FYP), namely Asynchronous Circuit Design Compiler. Asynchronous circuits have inherent advantages over synchronous circuits. In spite of these advantages, synchronous circuits remain dominant in the industry and asynchronous circuits remain largely an academic pursuit. One of the reasons for the poor adoption by the industry is the lack of mature Electronic Design Automation (EDA) tools in asynchronous circuit design. In this project, the use of COMPILER as an EDA tool and the proposed asynchronous circuit design flow utilising COMPILER is explored. Adhering to the asynchronous circuit design flow, an asynchronous 8-bit microprocessor is designed. Verilog HDL is used to express the designs. Apart from using COMPILER, EDA tools commonly used in the industry are also used to aid in the designing of the asynchronous 8-bit microprocessor. The process of designing involves specification, compilation, simulation, modules linking and analysis of circuit designs. A synchronous equivalent of the microprocessor is also designed for comparison purposes between synchronous circuit design flow and the asynchronous circuit design flow. The same EDA tools are used in the designing of the synchronous microprocessor. The design process is documented. Modifications and special constructs invoked to manipulate the asynchronous control channels are discussed.