VLSI based hardware accelerator for compute intensive routing applications
Identifying the most optimal paths (or routes) in a network is one of the most extensively studied problems in the field of graph theory. The advent of complex applications such as the VLSI place and route, vehicle navigation, high-speed communication, graph matching, dynamic robot path planning, et...
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sg-ntu-dr.10356-23402023-03-04T00:32:53Z VLSI based hardware accelerator for compute intensive routing applications Lam, Siew Kei Srikanthan, Thambipillai School of Computer Engineering DRNTU::Engineering::Computer science and engineering::Computer systems organization::Computer-communication networks Identifying the most optimal paths (or routes) in a network is one of the most extensively studied problems in the field of graph theory. The advent of complex applications such as the VLSI place and route, vehicle navigation, high-speed communication, graph matching, dynamic robot path planning, etc. justify the need to devise a high-speed route computation unit. It is well recognised that a significant improvement in performance could be realised if the route computations can be efficiently ported to hardware. Since the classical algorithms do not lend well for hardware porting, there exists a need to devise new techniques that are capable of providing parallelism at the hardware level. Doctor of Philosophy (SCE) 2008-09-17T09:00:25Z 2008-09-17T09:00:25Z 2000 2000 Thesis http://hdl.handle.net/10356/2340 Nanyang Technological University application/pdf |
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DRNTU::Engineering::Computer science and engineering::Computer systems organization::Computer-communication networks Lam, Siew Kei VLSI based hardware accelerator for compute intensive routing applications |
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Identifying the most optimal paths (or routes) in a network is one of the most extensively studied problems in the field of graph theory. The advent of complex applications such as the VLSI place and route, vehicle navigation, high-speed communication, graph matching, dynamic robot path planning, etc. justify the need to devise a high-speed route computation unit. It is well recognised that a significant improvement in performance could be realised if the route computations can be efficiently ported to hardware. Since the classical algorithms do not lend well for hardware porting, there exists a need to devise new techniques that are capable of providing parallelism at the hardware level. |
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Srikanthan, Thambipillai |
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Srikanthan, Thambipillai Lam, Siew Kei |
format |
Theses and Dissertations |
author |
Lam, Siew Kei |
author_sort |
Lam, Siew Kei |
title |
VLSI based hardware accelerator for compute intensive routing applications |
title_short |
VLSI based hardware accelerator for compute intensive routing applications |
title_full |
VLSI based hardware accelerator for compute intensive routing applications |
title_fullStr |
VLSI based hardware accelerator for compute intensive routing applications |
title_full_unstemmed |
VLSI based hardware accelerator for compute intensive routing applications |
title_sort |
vlsi based hardware accelerator for compute intensive routing applications |
publishDate |
2008 |
url |
http://hdl.handle.net/10356/2340 |
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1759858105852624896 |