Design of a 54x54-bit multiplier using radix-16 redundant binary booth encoding

Design of a 54x54-bit multiplier using radix-16 redundant binary booth encoding

In this project, some of these multiplying coefficients were chosen as fundamental multiplying coefficients, and any other multiplying coefficient could be represented as an RB number which consists of two of these fundamental multiplying coefficients or their inverses. The RB partial product genera...

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Main Author: Soh, Sing Yu.
Other Authors: Chang, Chip Hong
Format: Theses and Dissertations
Published: 2008
Subjects:
DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Online Access:http://hdl.handle.net/10356/3269
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Institution: Nanyang Technological University
id sg-ntu-dr.10356-3269
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spelling sg-ntu-dr.10356-32692023-07-04T15:42:39Z Design of a 54x54-bit multiplier using radix-16 redundant binary booth encoding Soh, Sing Yu. Chang, Chip Hong School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits In this project, some of these multiplying coefficients were chosen as fundamental multiplying coefficients, and any other multiplying coefficient could be represented as an RB number which consists of two of these fundamental multiplying coefficients or their inverses. The RB partial product generator (RBPPG) was used to generate RB partial products. These RB partial products were added in the RB adder (RBA) array block. Some of the RBA cells in the RBA circuit were optimised for the multiplier in this project. Master of Science (Integrated Circuit Design) 2008-09-17T09:26:00Z 2008-09-17T09:26:00Z 2006 2006 Thesis http://hdl.handle.net/10356/3269 Nanyang Technological University application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
topic DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
spellingShingle DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Soh, Sing Yu.
Design of a 54x54-bit multiplier using radix-16 redundant binary booth encoding
description In this project, some of these multiplying coefficients were chosen as fundamental multiplying coefficients, and any other multiplying coefficient could be represented as an RB number which consists of two of these fundamental multiplying coefficients or their inverses. The RB partial product generator (RBPPG) was used to generate RB partial products. These RB partial products were added in the RB adder (RBA) array block. Some of the RBA cells in the RBA circuit were optimised for the multiplier in this project.
author2 Chang, Chip Hong
author_facet Chang, Chip Hong
Soh, Sing Yu.
format Theses and Dissertations
author Soh, Sing Yu.
author_sort Soh, Sing Yu.
title Design of a 54x54-bit multiplier using radix-16 redundant binary booth encoding
title_short Design of a 54x54-bit multiplier using radix-16 redundant binary booth encoding
title_full Design of a 54x54-bit multiplier using radix-16 redundant binary booth encoding
title_fullStr Design of a 54x54-bit multiplier using radix-16 redundant binary booth encoding
title_full_unstemmed Design of a 54x54-bit multiplier using radix-16 redundant binary booth encoding
title_sort design of a 54x54-bit multiplier using radix-16 redundant binary booth encoding
publishDate 2008
url http://hdl.handle.net/10356/3269
_version_ 1772828632154112000

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