Macromodelling of analogue circuits using VHDL-AMS

• المؤلف الرئيسي: Su, Latt Mon.
• مؤلفون آخرون: Lam, Yvonne Ying Hung
• التنسيق: Theses and Dissertations
• منشور في: 2008
• الموضوعات: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• الوصول للمادة أونلاين: http://hdl.handle.net/10356/3298

The purpose of this project is to implement the top down design system by using VHDL-AMS. VHDL-AMS, an analogue hardware description language and an extension to Very High-Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL), is capable of modelling analogue models by using additio...