Fully-integrated CMOS building blocks for phase-locked loops in the multi-GHz range

The wireless communication industry is currently experiencing a tremendous growth. The frequency synthesizer, which is usually formed by a Phase-Locked Loop (PLL), is a major and critical component of a wireless transceiver. Currently, there exist several different standards of operation; thus a mul...

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Main Author: Yu, Xiaopeng
Other Authors: Lin Yiqun
Format: Theses and Dissertations
Published: 2008
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Online Access:https://hdl.handle.net/10356/3940
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Institution: Nanyang Technological University
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spelling sg-ntu-dr.10356-39402023-07-04T17:14:29Z Fully-integrated CMOS building blocks for phase-locked loops in the multi-GHz range Yu, Xiaopeng Lin Yiqun Do Manh Anh School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits The wireless communication industry is currently experiencing a tremendous growth. The frequency synthesizer, which is usually formed by a Phase-Locked Loop (PLL), is a major and critical component of a wireless transceiver. Currently, there exist several different standards of operation; thus a multi-standard frequency synthesizer is desirable for operations under different wireless systems. The objective of this project is to design the most critical building blocks for the multi-GHz frequency synthesizers. All proposed circuits are realized on cost effective CMOS technology. Two prescalers, implemented with the dynamic CMOS circuit and the imbalanced phase switching technique are proposed to achieve lower power consumption for a higher operating frequency. The GHz operation of all-stage programmable counter is first achieved in this work by proposing a new re-loadable bitcell. To achieve the multi-band operation, a VCO with a wide tuning range of 5-6 GHz and a good phase noise performance is designed. By combining with other low frequency building blocks, a complete 5-6 GHz frequency synthesizer is realized to cover both the IEEE 802.11a and the HIPERLAN II standards. DOCTOR OF PHILOSOPHY (EEE) 2008-09-17T09:40:49Z 2008-09-17T09:40:49Z 2006 2006 Thesis Yu, X. (2006). Fully-integrated CMOS building blocks for phase-locked loops in the multi-GHz range. Doctoral thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/3940 10.32657/10356/3940 Nanyang Technological University application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
topic DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
spellingShingle DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Yu, Xiaopeng
Fully-integrated CMOS building blocks for phase-locked loops in the multi-GHz range
description The wireless communication industry is currently experiencing a tremendous growth. The frequency synthesizer, which is usually formed by a Phase-Locked Loop (PLL), is a major and critical component of a wireless transceiver. Currently, there exist several different standards of operation; thus a multi-standard frequency synthesizer is desirable for operations under different wireless systems. The objective of this project is to design the most critical building blocks for the multi-GHz frequency synthesizers. All proposed circuits are realized on cost effective CMOS technology. Two prescalers, implemented with the dynamic CMOS circuit and the imbalanced phase switching technique are proposed to achieve lower power consumption for a higher operating frequency. The GHz operation of all-stage programmable counter is first achieved in this work by proposing a new re-loadable bitcell. To achieve the multi-band operation, a VCO with a wide tuning range of 5-6 GHz and a good phase noise performance is designed. By combining with other low frequency building blocks, a complete 5-6 GHz frequency synthesizer is realized to cover both the IEEE 802.11a and the HIPERLAN II standards.
author2 Lin Yiqun
author_facet Lin Yiqun
Yu, Xiaopeng
format Theses and Dissertations
author Yu, Xiaopeng
author_sort Yu, Xiaopeng
title Fully-integrated CMOS building blocks for phase-locked loops in the multi-GHz range
title_short Fully-integrated CMOS building blocks for phase-locked loops in the multi-GHz range
title_full Fully-integrated CMOS building blocks for phase-locked loops in the multi-GHz range
title_fullStr Fully-integrated CMOS building blocks for phase-locked loops in the multi-GHz range
title_full_unstemmed Fully-integrated CMOS building blocks for phase-locked loops in the multi-GHz range
title_sort fully-integrated cmos building blocks for phase-locked loops in the multi-ghz range
publishDate 2008
url https://hdl.handle.net/10356/3940
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