In-band phase noise reduction techniques for phase-locked loops in advanced CMOS technologies
Phase-locked loops (PLLs) have been successfully used as frequency synthesizers for decades in complementary metal–oxide–semiconductor (CMOS) transceivers for wireless communications. However, modern developments in communications require PLLs with wider loop bandwidth and lower in-band phase noise....
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| 格式: | Theses and Dissertations |
| 語言: | English |
| 出版: |
2018
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| 在線閱讀: | https://hdl.handle.net/10356/89075 http://hdl.handle.net/10220/46111 |
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| 機構: | Nanyang Technological University |
| 語言: | English |