Characterization of failure in integrated circuit due to electrostatic discharge (ESD)

• 主要作者: Goh, Jia Jun.
• 其他作者: Tan, Cher Ming
• 格式: Final Year Project
• 語言: English
• 出版: 2010
• 主題: DRNTU::Engineering
• 在線閱讀: http://hdl.handle.net/10356/40490

Electrostatic discharge (ESD) is the momentary electric current that flows between two objects of different electrical potentials. It is the result of static charge build-up on at least one of the objects, and this charge is often sufficiently large enough to cause catastrophic or latent defect failures to integrated circuits in the semiconductor industry. Despite advancements in ESD protection, ESD still affects production yields, manufacturing costs, product quality, reliability and profitability. In addition, as a result of electronic devices becoming faster and smaller in scale, their sensitivity to ESD has actually increased. Hence, it is apparent that more work needs to be done to investigate and characterize ESD failure in integrated circuits. With more foundries using automated component handling systems that reduce the need for human operators, it is clear that the focus needs to be based on a device level test, the Charged Device Model (CDM). CDM currents have risetimes that can be as fast as 100 picoseconds and pulse widths of less than 1 nanosecond wide, yet can have peak currents exceeding 10A. This high speed CDM event creates rapidly changing current and voltages in ESD protection circuits, thus understanding their high speed response is of great significance. Therefore, in addition to a CDM Tester that we will use in this project, we will utilize a Very Fast Transmission Line Pulse (VFTLP) machine to simulate the CDM event. By doing so, we hope to be able to find similarities and possible correlation between transistors zapped by CDM and VFTLP. Furthermore, by comparing I-V curves and photoemission between normal and silicon Nanowire Thin-Film Transistors (NWTFT), we seek to compare and contrast ESD damage caused by the two machines. Finally, by using these results, we hope to be able to refine current ESD failure characterization techniques to keep up with the evolving needs of the semiconductor industry.