Characterization of failure in integrated circuit due to electrostatic discharge (ESD)

Electrostatic discharge (ESD) is the momentary electric current that flows between two objects of different electrical potentials. It is the result of static charge build-up on at least one of the objects, and this charge is often sufficiently large enough to cause catastrophic or latent defect fai...

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Main Author: Goh, Jia Jun.
Other Authors: Tan, Cher Ming
Format: Final Year Project
Language:English
Published: 2010
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Online Access:http://hdl.handle.net/10356/40490
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-404902023-07-07T17:35:46Z Characterization of failure in integrated circuit due to electrostatic discharge (ESD) Goh, Jia Jun. Tan, Cher Ming School of Electrical and Electronic Engineering A*STAR SIMTech Kok, Shaw Wei DRNTU::Engineering Electrostatic discharge (ESD) is the momentary electric current that flows between two objects of different electrical potentials. It is the result of static charge build-up on at least one of the objects, and this charge is often sufficiently large enough to cause catastrophic or latent defect failures to integrated circuits in the semiconductor industry. Despite advancements in ESD protection, ESD still affects production yields, manufacturing costs, product quality, reliability and profitability. In addition, as a result of electronic devices becoming faster and smaller in scale, their sensitivity to ESD has actually increased. Hence, it is apparent that more work needs to be done to investigate and characterize ESD failure in integrated circuits. With more foundries using automated component handling systems that reduce the need for human operators, it is clear that the focus needs to be based on a device level test, the Charged Device Model (CDM). CDM currents have risetimes that can be as fast as 100 picoseconds and pulse widths of less than 1 nanosecond wide, yet can have peak currents exceeding 10A. This high speed CDM event creates rapidly changing current and voltages in ESD protection circuits, thus understanding their high speed response is of great significance. Therefore, in addition to a CDM Tester that we will use in this project, we will utilize a Very Fast Transmission Line Pulse (VFTLP) machine to simulate the CDM event. By doing so, we hope to be able to find similarities and possible correlation between transistors zapped by CDM and VFTLP. Furthermore, by comparing I-V curves and photoemission between normal and silicon Nanowire Thin-Film Transistors (NWTFT), we seek to compare and contrast ESD damage caused by the two machines. Finally, by using these results, we hope to be able to refine current ESD failure characterization techniques to keep up with the evolving needs of the semiconductor industry. Bachelor of Engineering 2010-06-16T02:46:29Z 2010-06-16T02:46:29Z 2010 2010 Final Year Project (FYP) http://hdl.handle.net/10356/40490 en Nanyang Technological University 77 p. application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic DRNTU::Engineering
spellingShingle DRNTU::Engineering
Goh, Jia Jun.
Characterization of failure in integrated circuit due to electrostatic discharge (ESD)
description Electrostatic discharge (ESD) is the momentary electric current that flows between two objects of different electrical potentials. It is the result of static charge build-up on at least one of the objects, and this charge is often sufficiently large enough to cause catastrophic or latent defect failures to integrated circuits in the semiconductor industry. Despite advancements in ESD protection, ESD still affects production yields, manufacturing costs, product quality, reliability and profitability. In addition, as a result of electronic devices becoming faster and smaller in scale, their sensitivity to ESD has actually increased. Hence, it is apparent that more work needs to be done to investigate and characterize ESD failure in integrated circuits. With more foundries using automated component handling systems that reduce the need for human operators, it is clear that the focus needs to be based on a device level test, the Charged Device Model (CDM). CDM currents have risetimes that can be as fast as 100 picoseconds and pulse widths of less than 1 nanosecond wide, yet can have peak currents exceeding 10A. This high speed CDM event creates rapidly changing current and voltages in ESD protection circuits, thus understanding their high speed response is of great significance. Therefore, in addition to a CDM Tester that we will use in this project, we will utilize a Very Fast Transmission Line Pulse (VFTLP) machine to simulate the CDM event. By doing so, we hope to be able to find similarities and possible correlation between transistors zapped by CDM and VFTLP. Furthermore, by comparing I-V curves and photoemission between normal and silicon Nanowire Thin-Film Transistors (NWTFT), we seek to compare and contrast ESD damage caused by the two machines. Finally, by using these results, we hope to be able to refine current ESD failure characterization techniques to keep up with the evolving needs of the semiconductor industry.
author2 Tan, Cher Ming
author_facet Tan, Cher Ming
Goh, Jia Jun.
format Final Year Project
author Goh, Jia Jun.
author_sort Goh, Jia Jun.
title Characterization of failure in integrated circuit due to electrostatic discharge (ESD)
title_short Characterization of failure in integrated circuit due to electrostatic discharge (ESD)
title_full Characterization of failure in integrated circuit due to electrostatic discharge (ESD)
title_fullStr Characterization of failure in integrated circuit due to electrostatic discharge (ESD)
title_full_unstemmed Characterization of failure in integrated circuit due to electrostatic discharge (ESD)
title_sort characterization of failure in integrated circuit due to electrostatic discharge (esd)
publishDate 2010
url http://hdl.handle.net/10356/40490
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